In recent years, electronic equipments are increasingly reduced in size and weight. According to this trend, reduction in size, weight and thickness as well as compounding are increasingly realized for the circuit substrates for use in such electronic equipments. In particular, high-frequency wireless communication devices including mobile phones utilize a multi-layer substrate using ceramics, based on, e.g., the excellent dielectric characteristics of the ceramics and the multi-layer technology. Recently, such a multi-layer substrate is increasingly reduced in size and thickness.
An electronic circuit group forming the electronic equipments such as the aforementioned wireless communication devices is used as a multi-layer substrate module formed on a multi-layer substrate. In such a multi-layer substrate module, not only an integrated circuit group is mounted on the top surface of the substrate, but also circuit elements are actively formed in a layer within the substrate, thereby forming an electronic circuit group using these circuit elements. Therefore, this is particularly advantageous for reduction in size and weight.
FIG. 18 is a cross-sectional view of a multi-layer substrate module illustrating a common arrangement example of electronic circuits in such a multi-layer substrate module.
Referring to FIG. 18, the multi-layer substrate module 100 is mounted on a main board 10, and receives supply of a reference potential Vss for grounding from an earth node 20 provided on the main board 10. The multi-layer substrate module 100 is a lamination of a plurality of insulating layers 105 formed from ceramics or the like.
The multi-layer substrate module 100 includes electronic circuits 210, 220, 230 therein. Hereinafter, the electronic circuits formed in the multi-layer substrate module 100 are sometimes simply referred to as internal circuits. Circuit elements forming the internal circuits are arranged in the insulating layers 105 or on the top surface of the multi-layer substrate module. In general, passive elements such as coils and resistors are formed within the insulating layers, and semiconductor elements such as transistors and diodes are mounted on the surface of the multi-layer substrate module as integrated circuits.
FIG. 18 exemplarily shows the case where the multi-layer substrate module is formed from three internal circuits 210, 220, 230. The internal circuit 210 includes circuit elements 211 and 212 formed in the insulating layers 105. Similarly, the internal circuit 220 includes a circuit element 221 that is an integrated circuit mounted on the multi-layer substrate module, and circuit elements 222, 223 formed in the insulating layers 105. The internal circuit 230 includes circuit elements 231, 232 and 233 formed in the insulating layers 105.
Although not specifically shown in the figure, the multi-layer substrate module 100 includes, as appropriate, pattern wirings for connecting these circuit elements. Transmission of electric signals between the multi-layer substrate module 100 and the main board 10 is conducted through signal transmission nodes 202 provided as, e.g., pin terminals. At least one of the signal transmission nodes is connected to the earth node 20 on the main board 10 in order to ground the multi-layer substrate module 100. Hereinafter, these signal transmission nodes are sometimes simply referred to as pin terminals 202, and the signal transmission node connected to the earth node is sometimes referred to as ground pin terminal 204 in order to distinguish it from the pin terminals 202.
A main ground line 150 connected to the ground pin terminal 204 is formed within the multi-layer substrate module 100 so as to extend through the insulating layers 105 in the vertical direction. Sub ground lines 215, 225, 235 are provided between the respective internal circuits and the main ground line 150. The main ground line 150 and the sub ground lines 215, 225, 235 electrically couple the respective internal circuits to the earth node 20 provided on the main board on which the multi-layer substrate module 100 is mounted, so that the internal circuits can receive supply of the reference potential Vss for grounding. Hereinafter, the main ground line and the sub ground lines are sometimes collectively referred to as a ground line group.
However, if the internal circuits provided in the multi-layer substrate module are circuits utilizing a high frequency, their operation stability may be degraded due to parasitic inductance of the ground line group.
FIG. 19 is a conceptual diagram illustrating the problems that occur in the internal circuits due to the parasitic inductance of the ground line group. FIG. 19 exemplarily shows the problems that occur between the internal circuits 210 and 220.
Referring to FIG. 19, the internal circuit 210 is electrically coupled to the earth node 20 through the sub ground line 215 and the main ground line 150. Similarly, the internal circuit 220 is connected to the earth node 20 through the sub ground line 225 and the main ground line 150. Provided that parasitic inductance of the main ground line 150 is Lgrd, impedance due to the parasitic inductance Lgrd, Z=ω·Lgrd (where ω=2·π·f; f is a frequency of a current), increases with increase in frequency.
Accordingly, in high-frequency operation, an earth current Igrd that is supposed to flow from the internal circuit 210 into the earth node 20 may possibly flow into another internal circuit 220 (Igrd′) through the sub ground line 225, rather than flowing through the main ground line 150 having high impedance.
Such an earth current Igrd flowing into another internal circuit as inflow current Igrd′ may possibly destabilize the operation of that internal circuit 220. Hereinafter, such a phenomenon as shown in FIG. 19 is sometimes referred to as an inflow phenomenon of the earth current.
In particular, such a problem greatly affects an internal circuit provided in the upper layer portion of the multi-layer substrate module that is subjected to increased parasitic inductance of the main ground line 150.
An integrated circuit mounted on a multi-layer substrate module such as a semiconductor chip has also suffered from the same problem.
FIG. 20 is a cross-sectional view showing a common arrangement example of a plurality of electronic circuits formed on a multi-layer substrate module.
Referring to FIG. 20, internal circuits 230 and 240 are integrated circuits including, e.g., semiconductor elements. In such an integrated circuit, a metal coating film for grounding is formed on its back surface, so that the integrated circuit is often grounded by the metal coating film.
For example, in the example of FIG. 22, the internal circuits 230 and 240, that is, integrated circuits, are respectively grounded by metal coating films 235 and 245.
In the case where the internal circuits 230 and 240 are integrally formed as a single chip on the multi-layer substrate module, the metal coating films 235 and 245 integrally serve as a single ground electrode. Accordingly, forming a sub ground line 255 between the integrated metal coating film 235, 245 and the main ground line 150 provided within the multi-layer substrate module 100 enables grounding of the internal circuits provided on the multi-layer substrate module.
However, the internal circuits 230 and 240 arranged as such may also be subjected to the inflow phenomenon of the earth current described in connection with FIG. 19 during high-frequency operation. This phenomenon is increased particularly for the internal circuits arranged on the multi-layer substrate module, due to the longer path length of the main ground line 150 and thus higher parasitic inductance Lgrd.
On the other hand, such a problem may also occur in a single internal circuit formed in the multi-layer substrate module. For example, a CDMA (Code Division Multiple Access)-based mobile phone uses a frequency band of about 1 to 2 GHz. However, components of such a mobile phone like a low noise amplifier (hereinafter, also referred to as a high-frequency amplifier circuit) and an orthogonal mixer may suffer from these problems.
FIG. 21 is a circuit diagram showing the structure of a common high-frequency amplifier circuit.
Referring to FIG. 21, the high-frequency amplifier circuit 300 includes a transistor 310 serving as an amplifying element, and resistive elements R1 to R4, capacitors C1 to C5 and an inductor L that are arranged around the transistor 310. These peripheral elements form a bias resistance, a coupling capacitance or the like for the transistor 310. A field effect transistor is exemplarily used as the transistor 310.
The high-frequency amplifier circuit 300 is driven by a driving potential Vdd, and amplifies a voltage signal applied to its input node IN for output to its output node OUT. Since the high-frequency amplifier circuit 300 is a commonly used circuit, detailed description of the operation thereof is omitted.
FIG. 22 is a conceptual diagram illustrating the problems that occur in the high-frequency amplifier circuit 300 due to the parasitic inductance of the ground lines.
Referring to FIG. 22, the peripheral elements (resistive elements, capacitors, and inductor) in FIG. 21 are shown as blocks 321 to 326. In the transistor 310, a current path is formed between the drain 312 and the source 313 according to an input to the gate 311. The potential level in response to the source-drain current appears at the output node OUT, whereby signal amplification is conducted.
In this case, the gate 311, drain 312 and source 313 of the transistor 310 are respectively connected to the main ground line 150 through the blocks 322, 324 and 325 as the peripheral elements so as to be grounded. In this case, as shown in FIG. 19, impedance due to the parasitic inductance Lgrd of the main ground line 150 is increased during high-frequency operation. Therefore, a drain current that is supposed to flow into the earth node 20 partially flows as an input to the gate 311 of the transistor 310. This phenomenon destabilizes the amplifying function of the transistor 310, whereby the high-frequency amplifier circuit 300 may possibly be rendered in an unstable state that is generally called “oscillation phenomenon”.
FIG. 23 is a block diagram showing arrangement of the orthogonal mixer.
Referring to FIG. 23, a 90° distributor 402 distributes a high-frequency signal RF (frequency frf) as a high-frequency signal RFI for I channel and a high-frequency signal RFQ for Q channel that have a phase difference of 90° from each other. A 0° distributor 404 distributes a local oscillation signal LO (frequency flo) as signals that are in phase with each other.
The orthogonal mixer 400 includes a first mixer 410a for I channel and a second mixer 410b for Q channel. The orthogonal mixer 400 receives the high-frequency signal RFI for I channel and the high-frequency signal RFQ for Q channel, which have a phase difference of 90° from each other, and the local oscillation signal LO to produce base band signals BBI and BBQ. The high-frequency signal RF corresponds to, e.g., a receiving wave in the mobile phones. The frequency flo of the local oscillation signal LO is half the frequency frf of the high-frequency signal RF.
The first mixer 410a produces the base band signal BBI (frequency |frf−flo|) based on the high-frequency signal RFI for I channel and the local oscillation signal LO. Similarly, the second mixer 410b receives the high-frequency signal RFQ for Q channel and the local oscillation signal LO to produce the base band signal BBQ (frequency |frf−flo|).
FIG. 24 is a waveform chart illustrating an ideal output signal of the orthogonal mixer.
Referring to FIG. 24, in an ideal state, the first mixer 410a and the second mixer 410b operate in a symmetric manner to produce the base band signals BBI and BBQ having the same amplitude and also having a phase difference of 90° from each other.
FIG. 25 is a conceptual diagram illustrating the problems that occur in the orthogonal mixer 400 due to the parasitic inductance of the ground lines.
It is now assumed that the orthogonal mixer 400 is formed within the multi-layer substrate module. In this case, when the first mixer 410a and the second mixer 410b are connected to the main ground line 150, the adverse effect resulting from the inflow of the earth current as described before is not caused by another internal circuit, but occurs between the first mixer 410a and the second mixer 410b in the orthogonal mixer circuit.
More specifically, as shown in FIG. 25, the earth current Igrd that is supposed to flow from, e.g., the first mixer 410a to the earth node 20 flows into the second mixer 410b through a current path shown by a dashed line due to the parasitic inductance Lgrd of the main ground line 150. This may possibly degrade orthogonality of both mixers. Due to the adverse effect of the inflow current Igrd′, an amplitude variation ΔA and a phase variation Δφ are produced between the base band signals BBI and BBQ, as shown in FIG. 26, resulting degraded orthogonal accuracy of the orthogonal mixer.